1. Technical Field
The present disclosure relates to an integrated circuit. More particularly, the present disclosure relates to a clock and data recovery circuit.
2. Description of Related Art
With the rapid development of manufacturing technology, the operating speed of integrated circuits has been significantly improved. In a high speed communication system, a clock and data recovery (CDR) circuit is commonly utilized for assuring that input data can be correctly read after being transferred.
Typically, a CDR circuit has a fixed bandwidth. To process data at a high speed, the bandwidth of the CDR circuit must be high to reduce offset of the input data efficiently. However, if the CDR circuit keeps the same operating speed when the offset of the input data is decreased, more noise from clock jitter may be introduced during the clock and data recovery operation.
Therefore, a heretofore-unaddressed need exists to address the aforementioned deficiencies and inadequacies.